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85211ami-01 www.icst.com/products/hiperclocks.html rev. a november 1, 2005 1 integrated circuit systems, inc. ics85211i-01 l ow s kew , 1- to -2 d ifferential - to -hstl f anout b uffer b lock d iagram p in a ssignment g eneral d escription the ics85211i-01 is a low skew, high perfor- mance 1-to-2 differential-to-hstl f anout buffer and a member of the hipercloc ks? f amily of high performance clock solutions from ics. the clk, nclk pair can accept most standard differential input levels. the ics85211 i-01 is characterized to operate from a 3.3v power supply. guaranteed output and part-to-part skew characteristics make the ics85211 i-01 ideal for those clock distribution applications demanding well defined performance and repeatability. for optimal performance, terminate all outputs. f eatures ? two differential hstl compatible outputs ? one differential clk, nclk input pair ? clk, nclk pair can accept the following differential input levels: lvds, lvpecl, hstl, sstl, hcsl ? maximum output frequency: 700mhz ? translates any single-ended input signal to hstl levels with resistor bias on nclk input ? output skew: 30ps (maximum) ? part-to-part skew: 250ps (maximum) ? propagation delay: 1ns (maximum) ? output crossover voltage: 0.68v to 0.9v ? output duty cycle: 49% - 51% up to 266.6mhz ? v oh = 1.4v (maximum) ? 3.3v operating supply ? -40c to 85c ambient operating temperature ? available in both standard and lead-free rohs-compliant packages hiperclocks? ic s ics85211i-01 8-lead soic 3.90mm x 4.90mm x 1.37mm package body m package top view q0 nq0 q1 nq1 1 2 3 4 v dd clk nclk gnd 8 7 6 5 q0 nq0 q1 nq1 clk nclk
85211ami-01 www.icst.com/products/hiperclocks.html rev. a november 1, 2005 2 integrated circuit systems, inc. ics85211i-01 l ow s kew , 1- to -2 d ifferential - to -hstl f anout b uffer t able 1. p in d escriptions t able 2. p in c haracteristics t able 3. c lock i nput f unction t able s t u p n is t u p t u o e d o m t u p t u o o t t u p n iy t i r a l o p k l ck l c n1 q , 0 q1 q n , 0 q n 00w o lh g i hl a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 11 h g i hw o ll a i t n e r e f f i d o t l a i t n e r e f f i dg n i t r e v n i n o n 01 e t o n ; d e s a i bw o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 11 e t o n ; d e s a i bh g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i n o n 1 e t o n ; d e s a i b0h g i hw o ll a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i 1 e t o n ; d e s a i b1w o lh g i hl a i t n e r e f f i d o t d e d n e e l g n i sg n i t r e v n i . " s l e v e l d e d n e e l g n i s t p e c c a o t t u p n i l a i t n e r e f f i d e h t g n i r i w " , n o i t c e s n o i t a m r o f n i n o i t a c i l p p a e h t o t r e f e r e s a e l p : 1 e t o n r e b m u ne m a ne p y tn o i t p i r c s e d 2 , 10 q n , 0 qt u p t u o. s l e v e l e c a f r e t n i l t s h . r i a p t u p t u o l a i t n e r e f f i d 4 , 31 q n , 1 qt u p t u o. s l e v e l e c a f r e t n i l t s h . r i a p t u p t u o l a i t n e r e f f i d 5d n gr e w o p. d n u o r g y l p p u s r e w o p 6k l c nt u p n i / p u l l u p n w o d l l u p . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n iv d d . g n i t a o l f t f e l n e h w t l u a f e d 2 / 7k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 8v d d r e w o p. n i p y l p p u s e v i t i s o p : e t o n n w o d l l u p d n a p u l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k
85211ami-01 www.icst.com/products/hiperclocks.html rev. a november 1, 2005 3 integrated circuit systems, inc. ics85211i-01 l ow s kew , 1- to -2 d ifferential - to -hstl f anout b uffer t able 4b. d ifferential dc c haracteristics , v dd = 3.3v 5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s r e w o p 5 3 1 . 33 . 35 6 4 . 3v i d d t n e r r u c y l p p u s r e w o p 2 2a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i k l c nv d d v = n i v 5 6 4 . 3 =0 5 1a k l cv d d v = n i v 5 6 4 . 3 =0 5 1a i l i t n e r r u c w o l t u p n i k l c nv d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a k l cv d d v , v 5 6 4 . 3 = n i v 0 =5 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c ; e g a t l o v t u p n i e d o m n o m m o c 2 , 1 e t o n 5 . 0v d d 5 8 . 0 -v v s i k l c n d n a k l c r o f e g a t l o v t u p n i m u m i x a m e h t s n o i t a c i l p p a d e d n e e l g n i s r o f : 1 e t o n d d . v 3 . 0 + v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . t able 4c. hstl dc c haracteristics , v dd = 3.3v 5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 0 . 14 . 1v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 04 . 0v v x o e g a t l o v r e v o s s o r c t u p t u o 8 6 . 09 . 0v v g n i w s g n i w s e g a t l o v t u p t u o k a e p - o t - k a e p 6 . 00 . 14 . 1v 0 5 h t i w d e t a n i m r e t e b t s u m s t u p t u o l l a : 1 e t o n . d n u o r g o t t able 4a. p ower s upply dc c haracteristics , v dd = 3.3v 5%, t a = -40c to 85c a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v dd -0.5v to v dd + 0.5 v outputs, v dd -0.5v to v dd + 0.5v package thermal impedance, ja 112.7c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
85211ami-01 www.icst.com/products/hiperclocks.html rev. a november 1, 2005 4 integrated circuit systems, inc. ics85211i-01 l ow s kew , 1- to -2 d ifferential - to -hstl f anout b uffer t able 5. ac c haracteristics , v dd = 3.3v 5%, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 0 7z h m t d p 1 e t o n ; y a l e d n o i t a g a p o r p? z h m 0 0 67 . 00 . 1s n t ) o ( k s4 , 2 e t o n ; w e k s t u p t u o 0 3s p t ) p p ( k s4 , 3 e t o n ; w e k s t r a p - o t - t r a p 0 5 2s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 20 0 5s p c d oe l c y c y t u d t u p t u o 8 42 5% ? z h m 6 . 6 6 29 41 5% . e s i w r e h t o d e t o n s s e l n u z h m 0 0 6 t a d e r u s a e m s r e t e m a r a p l l a . r e t t i j d d a t o n s e o d t r a p e h t . t u p t u o e h t n o r e t t i j e h t l a u q e l l i w t u p n i e h t n o r e t t i j e l c y c - o t - e l c y c e h t . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o t a d e r u s a e m d a o l l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n . s t n i o p s s o r c l a i t n e r e f f i d e h t t a d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n
85211ami-01 www.icst.com/products/hiperclocks.html rev. a november 1, 2005 5 integrated circuit systems, inc. ics85211i-01 l ow s kew , 1- to -2 d ifferential - to -hstl f anout b uffer clock outputs 20% 80% 80% 20% t r t f v sw i n g t pw t period t pw t period odc = x 100% nq0, nq1 q0, q1 t pd nclk clk nq0, nq1 q0, q1 qx nqx qy nqy pa rt 1 pa rt 2 t sk(pp) 3.3v o utput l oad ac t est c ircuit d ifferential i nput l evel p art - to -p art s kew o utput s kew o utput d uty c ycle /p ulse w idth /p eriod o utput r ise /f all t ime p ropagation d elay p arameter m easurement i nformation t sk(o) nqx qx nqy qy v cmr cross points v pp nclk clk gnd v dd scope hstl qx nqx 3.3v5% 0v v dd gnd
85211ami-01 www.icst.com/products/hiperclocks.html rev. a november 1, 2005 6 integrated circuit systems, inc. ics85211i-01 l ow s kew , 1- to -2 d ifferential - to -hstl f anout b uffer s chematic e xample figure 2 shows a schematic example of ics85211i-01. in this example, the input is driven by an ics hiperclocks hstl driver. the decoupling capacitors should be physically located near f igure 2. ics85211i-01 hstl b uffer s chematic e xample the power pin. for ics85211i-01, the unused outputs need to be terminated. a pplication i nformation figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 1. s ingle e nded s ignal d riving d ifferential i nput of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. w iring the d ifferential i nput to a ccept s ingle e nded l evels c1 0.1u r4 50 u1 ics85211-01 1 2 3 4 8 7 6 5 q0 nq0 q1 nq1 vdd clk nclk gnd zo = 50 ohm r3 50 r1 50 zo = 50 ohm 1.8v zo = 50 ohm r5 50 zo = 50 ohm lvhstl lvhstl driv er vdd=3.3v hiperclocks r2 50 ics unused output need to be term inat ed r6 50 lvhstl input + - v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vdd
85211ami-01 www.icst.com/products/hiperclocks.html rev. a november 1, 2005 7 integrated circuit systems, inc. ics85211i-01 l ow s kew , 1- to -2 d ifferential - to -hstl f anout b uffer c lock i nput i nterface the clk /nclk accepts differential input signals of both v swing and v oh to meet the v pp and v cmr input requirements. figures 3a to 3d show interface examples for the ics85211i-01 clock input driven by most common driver types. the input interfaces sug- gested here are examples only. please consult with the vendor f igure 3a. ics85211i-01 clk/ n clk i nput d riven by h i p er c lock s hstl d river 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk of the driver components to confirm the driver termination require- ment. for example in figure 3, the input termination applies for ics hiperclocks hstl drivers. if you are using an hstl driver from another vendor, use their termination recommendation. f igure 3b. ics85211i-01 clk/ n clk i nput d riven by 3.3v lvpecl d river (i nterface 1) f igure 3c. ics85211i-01 clk/ n clk i nput d riven by 3.3v lvpecl d river (i nterface 2) 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v f igure 3d. ics85211i-01 clk/ n clk i nput d riven by 3.3v lvpecl d river with ac c ouple r3 125 lvpecl r1 84 c1 r2 84 hiperclocks clk nclk r5,r6 locate near the driv er pin. zo = 50 ohm 3.3v 3.3v c2 r4 125 r6 100-200 zo = 50 ohm r5 100-200 3.3v input r ecommendations for u nused o utput p ins o utputs : hstl o utput all unused hstl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated.
85211ami-01 www.icst.com/products/hiperclocks.html rev. a november 1, 2005 8 integrated circuit systems, inc. ics85211i-01 l ow s kew , 1- to -2 d ifferential - to -hstl f anout b uffer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics85211i-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics85211i-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v dd_max * i dd_max = 3.465v * 22ma = 76.2mw ? power (outputs) max = 82.34mw/loaded output pair if all outputs are loaded, the total power is 2 * 82.34mw = 164.7mw total power _max (3.465v, with all outputs switching) = 76.2mw + 164.7mw = 240.9mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.241w * 103.3c/w = 110c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 153.3c/w 128.5c/w 115.5c/w multi-layer pcb, jedec standard test boards 112.7c/w 103.3c/w 97.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. t able 6. t hermal r esistance ja for 8- pin soic, f orced c onvection
85211ami-01 www.icst.com/products/hiperclocks.html rev. a november 1, 2005 9 integrated circuit systems, inc. ics85211i-01 l ow s kew , 1- to -2 d ifferential - to -hstl f anout b uffer 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. hstl output driver circuit and termination are shown in figure 4. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load. pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = (v oh_max /r l ) * (v dd_max - v oh_max ) pd_l = (v ol_max /r l ) * (v dd_max - v ol_max ) pd_h = (1.4v/50 ) * (3.465v - 1.4v) = 57.82mw pd_l = (0.4v/50 ) * (3.465v - 0.4v) = 24.52mw total power dissipation per output pair = pd_h + pd_l = 82.34mw f igure 4. hstl d river c ircuit and t ermination v dd v out rl 50 q1
85211ami-01 www.icst.com/products/hiperclocks.html rev. a november 1, 2005 10 integrated circuit systems, inc. ics85211i-01 l ow s kew , 1- to -2 d ifferential - to -hstl f anout b uffer r eliability i nformation t ransistor c ount the transistor count for ics85211i-01 is: 411 t able 7. ja vs . a ir f low t able for 8 l ead soic ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 153.3c/w 128.5c/w 115.5c/w multi-layer pcb, jedec standard test boards 112.7c/w 103.3c/w 97.1c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
85211ami-01 www.icst.com/products/hiperclocks.html rev. a november 1, 2005 11 integrated circuit systems, inc. ics85211i-01 l ow s kew , 1- to -2 d ifferential - to -hstl f anout b uffer p ackage o utline - m s uffix for 8 l ead soic t able 8. p ackage d imensions reference document: jedec publication 95, ms-012 l o b m y s s r e t e m i l l i m n u m i n i mm u m i x a m n8 a5 3 . 15 7 . 1 1 a0 1 . 05 2 . 0 b3 3 . 01 5 . 0 c9 1 . 05 2 . 0 d0 8 . 40 0 . 5 e0 8 . 30 0 . 4 ec i s a b 7 2 . 1 h0 8 . 50 2 . 6 h5 2 . 00 5 . 0 l0 4 . 07 2 . 1 0 8
85211ami-01 www.icst.com/products/hiperclocks.html rev. a november 1, 2005 12 integrated circuit systems, inc. ics85211i-01 l ow s kew , 1- to -2 d ifferential - to -hstl f anout b uffer t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are i mplied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extraordinary environment al requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or w arrant any ics product for use in life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 1 0 - i m a 1 1 2 5 8 s c i1 0 i a 1 1 2 5c i o s d a e l 8e b u tc 5 8 o t c 0 4 - t 1 0 - i m a 1 1 2 5 8 s c i1 0 i a 1 1 2 5c i o s d a e l 8l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l 1 0 - i m a 1 1 2 5 8 s c il 1 0 i a 1 1 2c i o s " e e r f - d a e l " d a e l 8e b u tc 5 8 o t c 0 4 - t f l 1 0 - i m a 1 1 2 5 8 s c il 1 0 i a 1 1 2c i o s " e e r f - d a e l " d a e l 8l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a r a h t s t r a p : e t o n the aforementioned trademark, hiperclocks is a trademark of integrated circuit systems, inc. or its subsidiaries in the united states and/or other countries.
85211ami-01 www.icst.com/products/hiperclocks.html rev. a november 1, 2005 13 integrated circuit systems, inc. ics85211i-01 l ow s kew , 1- to -2 d ifferential - to -hstl f anout b uffer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a 1 2 2 2 . l t s h o t l t s h v l d e g n a h c t e e h s a t a d t u o h g u o r h t v m o r f e p y t k l c n d e g n a h c d d . n w o d l l u p / p u l l u p o t 2 / c d e g n a h c - e l b a t s c i t s i r e t c a r a h c n i p n i . l a c i p y t f p 4 o t . x a m f p 4 r d e g n a h c p u l l u p r o t p u l l u p r / n w o d l l u p . s r o t s i s e r n w o d l l u p / p u l l u p , 3 0 / 6 1 / 7 a 9 t 1 7 2 1 . t e l l u b s h o r / e e r f d a e l d e d d a - n o i t c e s s e r u t a e f d e d d a . s n i p t u p t u o d e s u n u r o f s n o i t a d n e m m o c e r . g n i k r a m d n a r e b m u n t r a p e e r f - d a e l d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 5 0 / 1 0 / 1 1

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